Krishnaiyan Thulasiraman

Mathematical Theory of Multiport Resistance Networks

K. Thulasiraman, “On Description and Realization of Resistance n-port Networks”, IEEE Trans. on Circuits and Systems, Vol. CAS-32, March 1985, pp. 296-297.

K. Thulasiraman, M. N. S. Swamy and P. S. Reddy, “(N+P)-node Realizability of Y-Matrices of (N+1)-node Resistance Networks”, International Journal of Circuit Theory and Applications, Vol. 6, 1978, pp. 253-263.

P. S. Reddy and K. Thulasiraman, “Synthesis of the K-Matrix of (N+3)-node Resistive n-port Networks”, Z. Elektr. Inform. U. Energietechnik, Leipzig, 1978, pp. 86-92.

M. G. G. Naidu, P. S. Reddy and K. Thulasiraman, “Continuously Equivalent Realizations of 3rd-order Paramount Matrices”, International Journal of Circuit Theory and Applications, Vol. 5, 1977, pp. 403-408.

M. G. G. Naidu, P. S. Reddy and K. Thulasiraman, “On the Number of Conductances Required for Realizing Y and K Matrices”, International Journal of Circuit Theory and Applications, Vol. 5, 1977, pp. 219-225.

M. G. G. Naidu, P. S. Reddy and K. Thulasiraman, “(n+2)-node Resistive n-port Realizability of Y-Matrices”, IEEE Trans.on Circuits and Systems, Vol. CAS-23, May 1976, pp. 254- 261.

M. G. G. Naidu, P. S. Reddy and K. Thulasiraman, “Synthesis of Resistive Networks from Third Order Paramount Matrices”, IEEE Trans.on Circuits and Systems, Vol. CAS-22, Dec. 1975, pp. 937-943.

M. G. G. Naidu, K. Thulasiraman and M. N. S. Swamy, “The n-port Resistive Network Synthesis from Prescribed Sensitivity Coefficients”, IEEE Trans. On Circuits and Systems, Vol. CAS-22, June 1975, pp. 482-485.

P. S. Reddy and K. Thulasiraman, “Analysis and Synthesis of the K and Y Matrices of Resistive n-port Networks”, Z. Elektri. Inform. U. Energietechnik, Leipzig 5, 1975, pp. 81-96.

P. S. Reddy and K. Thulasiraman, “Synthesis of (n+2)-node Resistive n-Port Networks”, IEEE Trans. on Circuit Theory, Vol. CT-19, January 1972, pp. 20-25. Also see K. Thulasiraman and P. S. Reddy, “Synthesis of (n+2)-node Resistive n-port Networks”, Proc. IEEE International Symposium on Circuit Theory, 1970.

M. N. S. Swamy, and K. Thulasiraman, “A Sufficient Condition for the Synthesis of the K-Matrix of n-Port Networks”, IEEE Trans. on Circuit Theory, Vol. CT-19, July 1972, pp. 378-380.

P. S. Reddy and K. Thulasiraman, “Synthesis of K-Matrix of (n+1)-node Resistive n-port Networks”, Proc. Asilomar Conference on Circuits and Systems, November pp. 588- 590, 1971. See also Proc. Asilomar Conference on Circuits and Systems, 1971.

P. S. Reddy and K. Thulasiraman, “Synthesis of the K-matrix of an N-port Network and its Application to Y-matrix Synthesis”, Proc. IEEE Intl. symp. on Circuit Theory, 1970.

P. S. Reddy, V. G. K. Murti and K. Thulasiraman, “Realization of Modified Cut-Set Matrix and Applications”, IEEE Trans. on Circuit Theory, Vol. CT-17, November 1970, pp. 475-486. See also Proc. IEEE Intl. Symp. on Circuit Theory, 1969.

K. Thulasiraman and V. G. K. Murti, “The Modified Circuit Matrix of an n-port Network and its Applications”, IEEE Trans. on Circuit Theory, Vol. CT-16, February 1969, pp. 2-7.

K. Thulasiraman and V. G. K. Murti, “Synthesis Application of the Modified Cutset Matrix", Proc. IEE, London, Vol. 115, Sept. 1968, pp. 1269-1274.

K. Thulasiraman and V. G. K. Murti, “The Modified Cutset Matrix of an n-port Network”, Proc. IEE London, Vol. 115, Sept. 1968, pp. 1263-1268. See also Proc. International Symposium on Circuit Theory, 1968.

V. G. K. Murti and K. Thulasiraman, “Synthesis of a Class n-port Networks”, IEEE Trans. on Circuit Theory, Vol. CT-15, March 1968, pp. 54-64.

C. Eswaran and K. Thulasiraman, “Synthesis of a Class of Resistive 3-port Networks”, International Journal of Electronics, 1968 Vol 24 pp. 597-603.

K. Thulasiraman and V. G. K. Murti, “Pseudo-Series Combination of n-port Networks”, Proc. IEEE, Vol. 56, June 1968, pp. 1143-1144

K. Thulasiraman and V. G. K. Murti, “Parallel Connection of n-port Networks”, Proc. IEEE, Vol. 55, July 1967, pp. 1216-1217.

K. Thulasiraman and V. G. K. Murti, “Comments on ‘On Equivalence of Resistive n-Port Networks"”, IEEE Trans. on Circuit Theory, Vol. CT-14, September 1967, pp. 357-359.