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VLSI Physical Design
Dong Xiang, Kaiwei Li, Hideo Fujiwara and Krishnaiyan Thulasiraman, “Constraining Transition Propagation for Low Power Scan Testing Using a Two-Stage Scan Architecture”, IEEE Transactions on Circuits and Systems, Part II: Briefs, May 2007, pp. 450-454.
M. Kaufmann, S. Gao, and K. Thulasiraman, "An Algorithm for Steiner Trees in Grid Graphs and its Application to Homotopic Routing", Journal of Circuits, Systems and Computers. Vol. 6, 1996, pp. 1-14.
J. Lienig and K. Thulasiraman, “GASBOR: A New Genetic Algorithm for Switch-Box Routing in Integrated Circuits”, Journal of Circuits, Systems and Computers. Vol. 6, 1996, pp. 356-373. See also J. Lienig and K. Thulasiraman, “GASBOR: A Genetic Algorithm for Switch-Box Routing in Integrated Circuits”, Proc. AI ‘94 Workshop on Evolutionary Computation, Armidale, Australia, 1994, pp. 199-212.
A. Safir, B. Haroun, B. and K. Thulasiraman, "Floorplanning with Datapath Optimization", ISCAS Vol 1, May 1995 pp. 41 - 44
S. Gao, and K. Thulasiraman, "An Improved Rectilinear Steiner Tree Algorithm for Terminals Located on a Convex Polygon".
S. Gao and K. Thulasiraman, “A Parallel Algorithm for Floorplanning with Integrated Global Routing”, International Conference on High Performance Computing, December 1995, pp. 457-462.
S. Khanna, S. Gao and K. Thulasiraman, “Parallel Hierachical Global Routing for General Cell Layout”, Proceedings Fifth Great Lakes Symposium on VLSI, 1995, pp. 212-215.
R. P. Chalasani, K. Thulasiraman and M. A. Comeau, “Integrated VLSI Layout Computation and Wire Balancing on a Shared Memory Multiprocessor: Evaluation of a Parallel Algorithm”, Proc. International Symp. on Parallel Architectures, Algorithms and Networks, (ISPAN), December, 1994, Kanazawa, Japan, pp. 49-56.
J. Lienig and K. Thulasiraman, “A Genetic Algorithm for Channel Routing in VLSI Circuits”, Evolutionary Computation, Vol. 1, No. 4, 1994, pp. 293-331. Also see Proc. Seventh Intl. Conf. on VLSI Design, Calcutta, January 1994, pp. 133-136.
A. Safir, B. Haroun and K. Thulasiraman, “A Floorplanner Driven by Structural and Timing Constraints”, Proc. IEEE Intl. Symp. Circuits and Systems, London, May 1994.
M. K. Kaufmann, S. Gao and K. Thulasiraman, “On Steiner Minimal Trees in Grid Graphs and Its Application to VLSI Routing”, Proc. 5th Intl. Symposium on Algorithms and Computations, 1994, pp. 351-359.
K. Thulasiraman, R. P. Chalasani, P. Thulasiraman and M. A. Comeau, “Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and A Unified Approach to VLSI Layout Compaction and Wire Balancing”, Proc. IEEE VLSI Design ‘93, Bombay, Jan. 1993.
K. Thulasiraman, M. A. Comeau, R. P. Chalasani, A. Das and J. W. Atwood, “On the Design of a Parallel Algorithm for VLSI Layout Compaction”, ISCAS 1990, New Orleans, May 1990.
J. Lienig, K. Thulasiraman and M.N.S. Swamy, “Routing Algorithms for Multi-Chip Modules”, Proc. European Design Automation Conf., Hamburg, 1992, pp. 286-291.
K. Thulasiraman and R. Jayakumar, “Optimum Single-Row Routing with No Cross-Overs”, Canadian VLSI Conference, November 1985.