You will be familiar with the principles of Boolean logic from your architecture class(es). However when we come to consider real logic circuits, we have to worry about nitty gritty details of current and voltage which were treated abstractly in your earlier work.
Logic circuitry is constructed from active elements, for example and gates, connected together with conductors. With conventional binary logic, each conductor at a given time is conceptually in one of two given states, a high state or a low state. The terms "high" and "low", referring to a potential difference with ground, are used in preference to "true" and "false" because, while normally a high state corresponds to true and a low state corresponds to false, it is sometimes convenient to think in terms of "inverted logic" in which a high signal represents a false state and a low signal represents a true state. In tables which specify the behaviour of a given logic circuit, high and low states are denoted by H and L respectively.
Thus, commonly, a single logic variable is specified as a potential difference between a single conductor and ground, though if a signal is to be conveyed over a "long" distance, it is a good idea to have a logic variable specified as the potential difference between two lines devoted to that variable.
However it is clearly impossible for high and low states each to be represented by exactly one voltage. Indeed, it is desirable that a system built out of logic gates should be rather tolerant of imprecision in the voltage-levels that represent a given logic-value. This is not just a matter of the fact that precision costs money - even more importantly it costs time. A good way of thinking about a conductor which connects two logic-gates is to compare it to a trough of water. The output of one gate A is connected to the trough, and an input of the other (gate B) is also connected. If the water in the trough is initially at low level, and gate A wants to raise it to a high level, it will dump a lot of water in the trough. As a result, the water in the trough will be initially quite rough - the initial water dumped by A will pass along the trough as a wave, eventually arriving at B. The wave may even be reflected off the end of the trough, and travel back to A. The water will continue to be disturbed for quite a long time after the original activation of A.
A conductor into which a logic gate is "pouring" charge will behave in an analogous way (though the analogy can be taken too far - the equations governing water waves are different from those governing electro-magnetic waves). A wave of charge will propagate along the conductor, and may reflect off the end. Thus it will inevitably take a significant time for a gate to establish a given voltage at a remote point in the circuit.
Thus it is desirable merely from the point of view of speed of operation for logic gates to be happy to accept a range of input voltages. The behaviour of an ideal inverter (logic NOT) is shown in the diagram.
Using a 5 volt supply (which is the most common), the gate changes its output state from a High value of +5 volts to Low of 0 volts when the input voltage exceeds a threshold of 2.5 volts. Any other such gate "looking" at this output will be guaranteed to "see" a correct value after a sufficient length of time has elapsed for the waves-of-charge propagating along the conductor connecting them to have fallen to half their original amplitude. We can set a minimum value for this time if we remember that light in a vacuum travels roughly a foot (0.3 metres) in a nanosecond. The propagation of the signal along a conductor is slower than this - between 0.3 and 0.5 times the speed-of-light. Thus, if we consider the signals in an ordinary circuit board, we may reasonably expect that one gate B whose input is "looking" at the output of another gate A somewhere on the board will have a correct input signal within a few nanoseconds of A changing its output. To this must be added the time taken for gate B to modify its output in response to the change in input signal. This time ranges from 0.3ns for the very fastest logic available to 90ns for the slowest.
If we look at our transfer function, we observe that the slope of the curve which plots output voltage versus input voltage is very steep at the threshold, while being flat almost everywhere else. This means that a logic gate acts as a high gain amplifier around its threshold. For the correct functioning of digital circuits, it is important to minimise the amount of time that logic gates spend in the threshold region. The most important aspect of this need is to avoid leaving any input of a logic gate unconnected. For typically such an unconnected input will bias itself to around the threshold voltage, and in effect act as a tiny but effective antenna for responding to any signals present in the environment - a perfect recipe for creating a logic system that fails spasmodically.
The reasons that there isn't just one universal family of logic chips are historical and technological. Different techologies were developed at different dates, and today different technologies offer distinct advantages.
The most important qualitative technological difference between logic families is whether bipolar transistors or field-effect transistors are used. The other qualitative difference is in the semi-conductor material used.
The earliest logic families mostly used bipolar transistors. Of these, by far the most successful was the TTL family, where "TTL" stands for "Transistor -Transistor Logic". This family, as popularised by Texas Instruments, is usually known as the "74" series.
With a given technology, variations of performance can achieved by trading off one characteristic against another. In logic circuitry, the most important trade-off is that of speed versus power-consumption. To fill up with charge the conductor connecting two gates in a short time requires power . Let us recall that the energy required to charge a capacitor of size C farads is V2C. Now a load for a logic gate output might be 20pF (including the capacitance of the conductor and of the inputs of any gates to which it is connected). So a state-change required to charge a conductor up to 5V will cost us 25*20 = 500 picojoules. This is not a lot of energy! But consider how much power is involved if we are to accomplish the state-change in a nanosecond - power = energy/time, and 500*10-12/10-9 come out at 500mW, for a single gate. This is a lot of power if we consider that even a small logic system might contain dozens of gates.
However what we have calculated is the peak power necessary to achieve a state-change in a conductor. Most logic gates spend most of their time not undergoing transitions. So, from the point of view of system power consumption, the more important consideration is quiescent power consumption. It is in this aspect that bipolar logic is at a disadvantage, since the output state of a bipolar transistor (conducting/non-conducting) depends on there being a significant input current. Thus a bipolar logic gate will always consume power at a rate which is a significant proportion of its maximum power capability
Thus bipolar logic is subject to a high quiescent power consumption. Within the general TTL family, various sub-families have been established which exploit a trade-off between speed and power. Also, a significant technological advance, the use of Schottky-clamped logic which avoids driving its transistors into saturation, allowed the development of TTL logic of superior performance - either faster (the 74S... series) or the low-power 74LS series. Further improvements on these are the 74AS and 74ALS series.
The other major weakness of TTL logic is not so inherent in the use of bipolar transistors, but arises more from the early development of TTL. This weakness is that the logic threshold of TTL is rather low, typically at +1.3 volts, though the specifications state that it can vary between +0.8V and +2.0 volts. Given that the output of a TTL gate is not pulled all the way to ground, it is clear that the noise margin of TTL, that is the amount of electrical noise that TTL-based circuitry can tolerate without malfunction, is rather small. Along with this goes the fact that TTL logic gates have a low, and variable, input impedance. Of course, it would have been possible to design bipolar logic gates which did not exhibit these problems but at a cost of being able to get fewer devices on a chip, and perhaps of having slower devices.
Incidentally, you should note that the logic high state of a TTL gate is around 3.5V.
CMOS logic makes use of field effect transistors arranged with a complementary pair of N-channel and P-channel FET's used to drive each signal. It has major advantages over TTL, though, being more complicated to fabricate, it has come to the market later. Its advantages include:
Unless you need ultra-fast logic you will have no call to use other families. The fastest logic is based on gallium arsenide as a semiconductor, and can be clocked at 2.7 gigahertz. The fastest silicon-based logic family is ECL.
While you can, to a large extent, connect up logic gates of a given family on a single board just by following some quite simple rules, if you want to interface between different logic families, or use logic gates to drive external circuitry, or conversely use external circuitry to provide inputs to logic gates, you will need to have a deeper understanding of the behaviour of logic gates as electronic circuits.
Firstly, let's consider what a logic input looks like. A CMOS input is fairly straightforward. At DC the impedance is nearly infinite across the whole range from ground up to the supply voltage. Above and below that range the input is "clamped" to the supply by diodes, whose role is partly to protect the circuit against static electricity damage during manufacture. However clamping is also useful to absorb energy from signals that go momentarily outside the legal-range because of a rapid transition.
Of course, a CMOS input has capacitance which means in effect that it takes a minimum signal energy of a few pico-joules to operate such a gate. This capacitance would only be of concern if you wanted to design an embedded system which involved very fast input into CMOS logic.
As the figure shows, the input behaviour of a TTL gate is more complicated arising essentially from the fact that a bipolar transistor requires current to operate it.
A TTL input can be held at a logic high state with a small input current (never more than 20micro amps, usually less). However to keep a TTL input at a logic low state, the circuit that is driving it has to be able to sink nearly a milliamp, while keeping the input below 0.4 volts. So, for example, trying to drive a TTL gate from an emitter follower is a bad idea - current comes out of the input of the TTL gate, and can't go back the "wrong way" through the emitter of the resistor. Generally, a TTL input should be driven from some kind of switch to ground - a transistor switch will do, or a mechanical switch.
Let us now consider the transfer function - the relationship between input voltage and output voltage. We have already seen a diagram showing the ideal behaviour. The actual behaviour of logic families is illustrated in the figure:
The "pure" CMOS gates behave (at least nominally) very close to the ideal curve we drew earlier. However, TTL behaves in a way that is quite asymmetric. The TTL high is normally around 3.5 volts (but may be lower for within the specifications), while the TTL low is as much as 0.2 volts. Moreover, as discussed earlier, the TTL threshold is between 0.8 and 2 volts, depending on family and on individual devices.
If we want to make a logic gate do anything other than drive another gate of the same family, we also have to understand the output characteristics of the gate. Generally, logic gates can't directly do much in the outside world. Usually you need an amplifier external to the gate to achieve a big effect. However, careful choice of how you make a logic gate drive external components, based on an understanding of the characteristics of the gate, can lead to reliable, economic circuit design. The primary characteristics of a logic gate output are what its voltage level is when no current is passing through the output, and how that voltage varies with current being drawn. These characteristics are illustrated in the figure, redrawn from Horowitz and Hill. Not surprisingly, we find that the fastest logic families have the gentlest slopes (that is, they have a low output impedance), arising from the requirement upon them to deliver a lot of current to a conductor to raise or lower it fast .
The main points to note about this figure is the very poor current output capability of old-style CMOS, and the relatively poor current output capability of the low-power Schottky family of TTL. Also note that the logic low curves for most kinds of TTL are flatter than the logic high curves, or, to put it another way, most TTL is better at sinking current than sourcing it. So, if it's otherwise convenient, it's better to put a load between a TTL output and +5V, activating the load by a logic low, than it is to have the load between the output and ground.